description features ? esd interface capability for hbm standards - mil std 3015.7 ................................................. 15kv - iec 61000-4-2, direct discharge, - single input .......................................... 4kv (level 2) - two inputs in parallel ............................ 8kv (level 4) - iec 61000-4-2, air discharge ............... 15kv (level 4) ? high peak current capability - iec 61000-4-5 (8/20s) ....................................... 3a - single pulse, 100s pulse width ........................ 2a - single pulse, 4s pulse width ............................ 5a ? designed to provide over-voltage protection - single-ended voltage range to ........................ +30v - differential voltage range to ............................ 15v ? fast switching ............................................. 2ns rise time ? low input leakages ............................ 1na at 25oc typical ? low input capacitance ..................................... 3pf typical ? an array of 6 scr/diode pairs ? operating temperature range .................... -40oc to 105oc applications the sp721 is an array of scr/diode bipolar structures for esd and over-voltage protection to sensitive input circuits. the sp721 has 2 protection scr/diode device structures per input. there are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. over- voltage protection is from the in (pins 1 - 3 and pins 5 - 7) to v+ or v-. the scr structures are designed for fast triggering at a threshold of one +v be diode threshold above v+ (pin 8) or a -v be diode threshold below v- (pin 4). from an in input, a clamp to v+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one v be above v+. a similar clamp to v- is activated if a negative pulse, one v be less than v-, is applied to an in input. standard esd human body model (hbm) capability is: ? microprocessor/logic input protection ? data bus protection ? analog device input protection ? voltage clamp pinout functional block diagram 4 v+ v- in 3, 5-7 in in 1 8 2 sp721 (pdip, soic) top view in in in v- 1 2 3 4 8 7 6 5 v+ in in in rohs pb green sp721 series 3pf 4kv diode array additional information datasheet resources samples ? 2013 littelfuse, inc. specifcations are subject to change without notice. revised: 04/24/13 tvs diode arrays (spa ? diodes) general purpose esd protection - sp721 series
absolute maximum ratings parameter rating units continuous supply voltage, (v+) - (v-) +35 v forward peak current, i in to v cc , i in to gnd (refer to figure 5) 2, 100s a electrical characteristics t a = -40 o c to 105 o c, v in = 0.5v cc , unless otherwise specifed thermal information parameter rating units thermal resistance (typical, note 1) ja o c/w pdip package 160 o c/w soic package 170 o c/w maximum storage temperature range -65 to 150 o c maximum junction temperature (plastic package) 150 o c maximum lead temperature (soldering 20-40s)(soic lead tips only) 260 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. parameter symbol test conditions min typ max units operating voltage range, v supply - 2 to 30 - v v supply = [(v+) - (v-)] forward voltage drop in to v- v fwdl i in = 1a (peak pulse) - 2 - v in to v+ v fwdh - 2 - v input leakage current i in -20 5 +20 na quiescent supply current i quiescent - 50 200 na equivalent scr on threshold note 3 - 1. 1 - v equivalent scr on resistance v fwd /i fwd ; note 3 - 1 - input capacitance c in - 3 - pf input switching speed t on - 2 - ns note: esd ratings and capability (figure 1, table 1) load dump and reverse battery (note 2) 1. ja is measured with the component mounted on an evaluation pc board in free air. notes: 2. in automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. when the v+ and v- pins are connected to het same supply voltage source as the device or control line under protection, a current limiti ng resistor should be connected in series between the external supply and the sp721 supply pins to limit reverse battery current to within the rated maximum limits. bypass capacitors of typically 0.01f or larger romf the v+ and v- pins to ground are recommended. 3. refer to the figure 3 graph for defnitions of equivalent scr on threshold and scr on resistance. these characteristics are given here for thumb-rule nformation to determine peak current and dissipation under eos conditions. figure 4. t ypical applica tion of the sp721 as an input clamp for o ver-v ol ta ge, grea ter than 1v be abo ve v+ or less than -1v be bel ow v- +v cc input driver s sp721 input pr o tection circuit (1 of 6 sho wn) or signal sources in 5 - 7 in 1 - 3 sp721 v- to +v cc linear or digit al ic interf ac e v+ +v cc (application as an input clamp for over-voltage, greater than 1v be above v+ or less than -1v be below v-) typical application of the sp721 ? 2013 littelfuse, inc. specifcations are subject to change without notice. revised: 04/24/13 tvs diode arrays (spa ? diodes) general purpose esd protection - sp721 series
esd capability esd capability is dependent on the application and defned test standard.the evaluation results for various test standards and methods based on figure 1 are shown in table 1. for the modifedmil-std-3015.7 condition that is defned as an in-circuit method of esd testing, the v+ and v- pins have a return path to ground and the sp721 esd capability is typically greater than 15kv from 100pf through 1.5k.by strict defnition of mil-std-3015.7 using pin-to-pindevice testing, the esd voltage capability is greater than 6kv.the mil-std-3015.7 results were determined from at&t esd test lab measurements. the hbm capability to the iec 61000-4-2 standard is greater than 15kv for air discharge (level 4) and greater than 4kv for direct discharge (level 2).dual pin capability (2 adjacent pins in parallel) is well in excess of 8kv (level 4). for esd testing of the sp721 to eiaj ic121 machine model (mm) standard, the results are typically better than 1kv from 200pf with no series resistance. standard type/mode r d c d v d mil std 3015.7 modifed hbm 1.5k 100pf 15kv standard hbm 1.5k 100pf 6kv iec 61000-4-2 hbm, air discharge 330 150pf 15kv hbm, direct discharge 330 150pf 4kv hbm, direct discharge, two parallel input pins 330 150pf 8kv eiaj ic121 machine model 0k 200pf 1kv h.v . suppl y v d in dut c d r 1 iec 1 000-4-2: r 1 50 t o 1 00 m r d charge switch discharge switch mil -s td-30 15.7: r 1 1 t o 1 0m 10 0 80 60 40 20 0 t a = 25oc single pulse 2.5 2 1. 5 1 0.5 0 v fwd i fwd equiv . sa t. on threshold ~ 1 .1v 60 0 80 0 1 000 12 00 for w ard scr vo lta ge drop (mv) for w ard scr current (ma) 0 1 2 3 for w ard scr current (a) for wa rd sct vo lta ge drop (v ) t a = 25oc single pulse 10 0 80 60 40 20 0 t a = 25oc single pulse 2.5 2 1. 5 1 0.5 0 v fwd i fwd equiv . sa t. on threshold ~ 1 .1v 60 0 80 0 1 000 12 00 for w ard scr vo lta ge drop (mv) for w ard scr current (ma) 0 1 2 3 for w ard scr current (a) for wa rd sct vo lta ge drop (v ) t a = 25oc single pulse figure 1: electrostatic discharge test table 1: esd test conditions figure 3: high current scr forward voltage drop curve figure 2: low current scr forward voltage drop curve ? 2013 littelfuse, inc. specifcations are subject to change without notice. revised: 04/24/13 tvs diode arrays (spa ? diodes) general purpose esd protection - sp721 series
peak transient current capability of the sp721 the peak transient current capability rises sharply as the width of the current pulse narrows. destructive testing was done to fully evaluate the sp721s ability to withstand a wide range of peak current pulses vs time. the circuit used to generate current pulses is shown in figure 4. the test circuit of figure 4 is shown with a positive pulse input. for a negative pulse input, the (-) current pulse input goes to an sp721 in input pin and the (+) current pulse input goes to the sp721 v- pin. the v+ to v- supply of the sp721 must be allowed to foat. (i.e., it is not tied to the ground reference of the current pulse generator.) figure 5 shows the point of overstress as defned by increased leakage in excess of the data sheet published limits. the maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. peak current curves are shown for ambient temperatures of 25oc and 105oc and a 15v power supply condition. the safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of figure 5. note that adjacent input pins of the sp721 may be paralleled to improve current (and esd) capability. the sustained peak current capability is increased to nearly twice that of a single pin. + - vo lt ag e pr obe + - r 1 ~ 1 0 t ypical v x v x adj . 1 0v/a t ypical r 1 (-) (+) c1 ~ 1 00 f c1 v ariable time dura tion current pulse genera to r 1 2 3 4 8 7 6 5 v+ in in in in in in v- sp721 current sense figure 5. t ypical sp721 peak current tes t circuit with a v ariable pulse width input 0.0 01 0.0 1 0.1 1 10 7 6 5 4 3 2 1 0 10 0 1 000 ca ution: safe opera ting conditions limit the maximum peak current for a given pulse width t o be no grea ter than 75% of the v alues sho wn on ea ch cur ve. v+ to v -suppl y = 15v t a = 25c t a = 1 05c pulse width time (ms) peak current (a) showing the measured point of overstress in amperes vs pulse width time in milliseconds figure 5: sp721 typical single peak current pulse capability figure 4: typical sp721 peak current test circuit with a variable pulse width input ? 2013 littelfuse, inc. specifcations are subject to change without notice. revised: 04/24/13 tvs diode arrays (spa ? diodes) general purpose esd protection - sp721 series
package dimensions dual-in-line plastic packages (pdip) ti me te mperature t p t l t s(max) t s(min) 25 t p t l t s time to peak temperature preheat p rehea t ramp-up r amp-up ramp-down r amp-d o critical zone t l to t p c ritical zo n e t l to t p refow condition pb C free assembly pre heat - temperature min (t s(min) ) 150c - temperature max (t s(max) ) 200c - time (min to max) (t s ) 60 C 180 secs average ramp up rate (liquidus) temp (t l ) to peak 5c/second max t s(max) to t l - ramp-up rate 5c/second max refow - temperature (t l ) (liquidus) 217c - temperature (t l ) 60 C 150 seconds peak temperature (t p ) 260 +0/-5 c time within 5c of actual peak temperature (t p ) 20 C 40 seconds ramp-down rate 5c/second max time 25c to peak temperature (t p ) 8 minutes max. do not exceed 260c soldering parameters c l e e a c e b e c -b- e1 index 12 3 n/2 n area sea ting ba se plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a - 0.0 1 0 (0.25) ca m bs no tes: 1. controlling dimensions: inch. in case of con?ict between english and metric dimensions, the inc h dimensions control. 2. dimensioning and tolerancing per ansi y1 4.5m -1 982. 3. s ymbols are de?ned in the ?mo s eries s ymbol list? in s ection 2.2 of p ublication no. 95. 4. dimensions a, a1 and l are measured with the pac k age seated in jedec seating plane g auge gs -3. 5. d, d1, and e1 dimensions do not include mold ?ash or protru- sions. mold ?ash or protrusions shall not exceed 0.010 inc h (0.25mm). 6. e and are measured with the leads constrained to be per - pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be z ero or greater . 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inc h (0.25mm). 9. n is the maximum number of terminal positions. 10 . corner leads (1, n, n/2 and n/2 + 1) for e8.3, e1 6.3, e1 8.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inc h (0.7 6 - 1. 1 4mm). e a -c- notes: 1. controlling dimensions: inch. in case of confict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. symbols are defned in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs-3. 5. d, d1, and e1 dimensions do not include mold fash or protrusions. mold fash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and e a are measured with the leads constrained to be perpendicular to datum -c- . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is t he maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). package pdip pins 8 lead dual-in-line jedec ms-001 millimeters inches notes min max min max a - 5.33 - 0.210 4 a1 0.39 - 0.015 - 4 a2 2.93 4.95 0.115 0.195 - b 0.356 0.558 0.014 0.022 - b1 1. 15 1.77 0.045 0.070 8, 10 c 0.204 0.355 0.008 0.014 - d 9.01 10.16 0.355 0.400 5 d1 0.13 - 0.005 - 5 e 7.62 8.25 0.300 0.325 6 e1 6.10 7. 11 0.240 0.280 5 e 2.54 bsc 0.100 bsc - e a 7.62 bsc 0.300 bsc 6 e b - 10.92 - 0.430 7 l 2.93 3.81 0.115 0.150 4 n 8 8 9 ? 2013 littelfuse, inc. specifcations are subject to change without notice. revised: 04/24/13 tvs diode arrays (spa ? diodes) general purpose esd protection - sp721 series
part numbering system lead plating matte tin lead material copper alloy lead coplanarity 0.004 inches (0.102mm) substitute material silicon body material molded epoxy flammability ul 94 v-0 product characteristics ordering information package dimensions small outline plastic packages (soic) notes: 1. symbols are defned in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. dimension d does not include mold fash, protrusions or gate burrs. mold fash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead fash or protrusions. inter-lead fash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. package soic pins 8 jedec ms-012 millimeters inches notes min max min max a 1.35 1.75 0.0532 0.0688 - a1 0.10 0.25 0.0040 0.0098 - b 0.33 0.51 0.013 0.020 9 c 0.19 0.25 0.0075 0.0098 - d 4.80 5.00 0.1890 0.1968 3 e 3.80 4.00 0.1497 0.1574 4 e 1.27 bsc 0.050 bsc - h 5.80 6.20 0.2284 0.2440 - h 0.25 0.50 0.0099 0.0196 5 l 0.40 1.27 0.016 0.050 6 n 8 8 7 0o 8o 0o 8o - index area e d n 12 3 -b- 0.25(0.0 10 )c a m bs e -a - l b m -c- a1 a sea ting plane 0.1 0(0.0 04) h x 45 o c h 0.25(0.0 10 )b m m no tes: 1. s ymbols are de?ned in the ?mo s eries s ymbol list? in s ection 2.2 of p ublication number 95. 2. dimensioning and tolerancing per ansi y1 4.5m -1 982. 3. dimension ?d? does not include mold ?ash, protrusions or g ate bur r s. mold ?ash, protrusion and g ate bur rs shall not exceed 0.1 5mm (0.0 06 inc h) per side. 4. dimension ?e? does not include interlead ?ash or protrusions. inter - lead ?ash and protrusions shall not exceed 0.25mm (0.010 inc h) per side. 5. the c hamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatc hed area. 6. ?l ? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. t erminal number s are shown for reference only . 9. the lead width ?b? , as measured 0.36mm (0.0 14 inc h) or greater abo ve the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inc h). 10 . controlling dimension: millimeter. con ver ted inc h dimensions are not necessarily exact. part number temp. range (oc) package environmental informaton marking min. order sp721app -40 to 105 8 ld pdip lead-free sp721ap(p) 1 2000 sp721abg -40 to 105 8 ld soic green sp721a(b)g 2 1960 sp721abtg -40 to 105 8 ld soic tape and reel green sp721a(b)g 2 2500 sp 721 series package p = lead free tg= tape and reel ab = 8 ld soic ap = 8 ld pdip g = green tvs diode arrays (spa ? diodes) ** ** notes: 1. sp721ap(p) means device marking either sp721ap or sp721app. 2. sp721a(b)g means device marking either sp721ag or sp721abg which are good for types sp721abg and sp721abtg. ? 2013 littelfuse, inc. specifcations are subject to change without notice. revised: 04/24/13 tvs diode arrays (spa ? diodes) general purpose esd protection - sp721 series
|
